project:hgg:timing_and_synchronization:dcf77
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende ÜberarbeitungLetzte ÜberarbeitungBeide Seiten der Revision | ||
project:hgg:timing_and_synchronization:dcf77 [2011-12-29 19:35] – reloc0 | project:hgg:timing_and_synchronization:dcf77 [2011-12-30 10:13] – reloc0 | ||
---|---|---|---|
Zeile 65: | Zeile 65: | ||
Then it does not realise the minute ended at all... | Then it does not realise the minute ended at all... | ||
+ | |||
+ | ===== And now for some nice imagery ===== | ||
+ | |||
+ | images of the signal we expected (top line) and the signal we got (bottom one) can be found in this schematic. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | As you can see, the fails of the module in a bad place can greatly screw up reading the signal. | ||
====== Description of the Algorithm ====== | ====== Description of the Algorithm ====== |
project/hgg/timing_and_synchronization/dcf77.txt · Zuletzt geändert: 2012-05-12 17:44 von 93.231.147.84