Unterschiede

Hier werden die Unterschiede zwischen zwei Versionen angezeigt.

--- project:hgg:project:hgg:hardware:timing_bus [2012-01-08 05:24] – 85.179.246.183
+++ project:hgg:project:hgg:hardware:timing_bus [2012-01-08 05:26] – 85.179.246.183
@@ Zeile 19: / Zeile 19: @@
 ===== High accuracy =====
-The high accuracy timing port will be sending a 10Mhz (currently wip, actual frequency to discuss) clock that is highly stabelized to all modules. It will also send a RESET port. Every measurement module will track the timing clock and count the clocks in a register (use 24 bit for 10Mhz). The reset pin will be used to reset the 24 bit register to 0. It will be triggered by the timing module every second. Thus we have a very exact pulse every 1 second and can use the contents of the register to count on in the 1 second timeframe.
+The high accuracy timing port will be sending a 10Mhz (currently wip, actual frequency to discuss) clock that is highly stabelized to all modules. It will also send a RESET signal. Every measurement module will track the timing clock and count the clocks in a register (use 24 bit for 10Mhz). The reset pin will be used to reset the 24 bit register to 0. It will be triggered by the timing module every second. Thus we have a very exact pulse every 1 second and can use the contents of the register to count on in the 1 second timeframe.
 To get the most accurate timing information, the measurement module will put a pin to high and the timing logic will copy the actual timing information into a buffer where it can be read from serially.
@@ Zeile 42: / Zeile 42: @@
   * for messuring the modules will send the timestamp (low precisision signal), the counter in the PISO and he most current drift information.
   * better timng modules could use a temperature and voltage controlled oscilator to make a more stable synchronisation signal
+===== Optimisatin =====
+  * FPGA/CPLD instead of discrete logic