project:hgg:hardware:timing_bus
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
| Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
| project:hgg:project:hgg:hardware:timing_bus [2012-01-08 05:25] – 85.179.246.183 | project:hgg:hardware:timing_bus [2017-11-09 02:06] (aktuell) – ↷ Seite von project:hgg:project:hgg:hardware:timing_bus nach project:hgg:hardware:timing_bus verschoben makefu | ||
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| The timing bus will consist of two parts, a high accuracy timing line and a low accuracy timing port. Low- and High Accuracy timestamps will be transmitted separately. | The timing bus will consist of two parts, a high accuracy timing line and a low accuracy timing port. Low- and High Accuracy timestamps will be transmitted separately. | ||
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| * for messuring the modules will send the timestamp (low precisision signal), the counter in the PISO and he most current drift information. | * for messuring the modules will send the timestamp (low precisision signal), the counter in the PISO and he most current drift information. | ||
| * better timng modules could use a temperature and voltage controlled oscilator to make a more stable synchronisation signal | * better timng modules could use a temperature and voltage controlled oscilator to make a more stable synchronisation signal | ||
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| + | ===== Optimisatin ===== | ||
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| + | * FPGA/CPLD instead of discrete logic | ||
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project/hgg/hardware/timing_bus.txt · Zuletzt geändert: 2017-11-09 02:06 von makefu