project:hgg:hardwaredoc:how_the_timing_bus_works
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Nächste Überarbeitung | Vorhergehende Überarbeitung | ||
project:hgg:hardwaredoc:how_the_timing_bus_works [2012-03-17 20:55] – angelegt reloc0 | project:hgg:hardwaredoc:how_the_timing_bus_works [2012-10-03 18:53] (aktuell) – alte Version wieder hergestellt 109.192.98.64 | ||
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- | If some module does not need the fasttime information becuase the developer feels that a 1 second resolution is good enough, it can recieve this packet into a 40-bit register. | + | If some module does not need the fasttime information becuase the developer feels that a 1 second resolution is good enough, it can recieve this packet into a 40-bit register. |
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Within a Ground-station the speed of the oscilator should be known and can assumed to be constant but clock drifts. | Within a Ground-station the speed of the oscilator should be known and can assumed to be constant but clock drifts. | ||
+ | ===== PPS - a new second begins ===== | ||
+ | When the PPS is activated (Active Low), the previously sent slowtime becomes valid. The local counters for the fastclock should be resetted. | ||
+ | ====== Measuring the Time with the Timing bus ====== | ||
+ | This describes how it would be for a Fast-Timing Module, for a module needing only the slow time information, | ||
+ | Prerequisites: | ||
+ | * There is a +1 Counter with 32 bits that counts up on every clock tick of the FASTCLK. | ||
+ | * The SLOWCLK Information is being put into a Register | ||
+ | * When PPS comes, the counter is being reseted and restarts from 0. The SLOWCLK Information from the Bus is latched into a register CURTIME. | ||
+ | When the event comes in, the following is happening: | ||
+ | - Latch CURTIME + the current Value of the Counter into a Parallel-in-Serial-Out Register (makes 72+32 bit). | ||
+ | - Process the event | ||
+ | - Get the Information from the PISO | ||
+ | - Send all information to the target over the | ||
+ | What you get is a 40-bit timestamp of the current time and the number of clock ticks within the current second. With a known FASTCLK frequency you can easily calculate the fraction of a second and thus complete the timestamp to SECOND and FRACTION OF SECOND values. | ||
+ | The maximum resoltution is dependent on the oscilator speed. Eg: 10Mhz FASTCLOCK makes 100ns resolution. | ||
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project/hgg/hardwaredoc/how_the_timing_bus_works.1332014106.txt.gz · Zuletzt geändert: 2012-03-17 20:55 von reloc0