All groundstations need to be timing synchronized. To achieve that, the timing module is used. The timing module will recieve timing data from a timesource and feed the timing bus in the groundstation. Every groundstation must only have 1 timing module but there's nothing enforce that (meaning it just will not work if two timing modules are installed). The timing module can usually also give us the position of the station (when using gps, galileo et al).

The timing information is split into three components:

1. PPS (pulse per second) … informs the modules about the begin of the next second
2. SLOWTIME … contains the timing information on a second base as a unix timestamp (
3. FASTCLOCK … contains the high precision timing information that hint the fraction of the current second.

The timing module will in always way contain theese components:

1. a timesource we call TIMESOURCE (in the current designs we use GPS)
2. a microcontroller we call MICROCONTROLLER (to configure the timesource)
3. a fast oscillator we call OSCILATOR to supply the fastclock output
4. a 32-bit counter named COUNTER to count the clock ticks of the OSCILATOR
5. a 40-bit serial-in-parallel-out spi register we call SLOWTIME_IN for recieving the slow timing information
6. two latches, 40- and 32-bit called SLOWTIME_LATCH and FASTCLOCK_LATCH
7. a 72-bit parallel-in-serial-out spi register called SLOWTIME_OUT

let me say, that the registers, latches, etc could be made entirely from discrete 74-ICs but imagining it is creepy. Thus we decided to use an FPGA here (CPLDs that contain enough registers are very expensive).

See this picture. It shows a drawn schematic of the timing bus with measurement modules and a timing module.

For the view of slowtime:

1. The TIMESOURCE pps pin goes up. The COUNTER (n in the image) is being latched into the latch register (n|m in the image) and reseted. This happens at the same time.
2. The MICROCONTROLLER begins to send the slowtime information on the next second to the SLOWTIME_IN register (m in the image).
3. When the SLOWTIME_IN register is filled with the slowtime, it is latched into the m part of the latch.
4. SLOWTIME_LATCH and FASTCLOCK_LATCH (m|n in the image) are being latched into the SLOWTIME_OUT register (? in the image)
5. SLOWTIME_OUT begins to spi the timing information on the bus
6. a bit less than a second goes by
7. The TIMESOURCE pps pin goes up. …

For the view of the fastclock:

The OSCILATOR generates a clock signal on the FASTCLOCK pins of the timing bus. All modules and the counter register count the number of clock cycles. After the pps pin on the TIMESOURCE goes up, the registers are cleared. The timing module stores the value at the end of the last second to measure the drifting properties of the oscilator.

What we got from this is, that at the beginning of a second, all the modules are told what the timestamp of the next second is and how much the fastclock has drifted in the last second. The measurement modules that recieve this information can use the sent slowtime information after recieving the PPS since it will be valid then.

For more information on the timing bus information, please see the article How the timing bus works.

The FPGA contains all the registers mentioned above, meaning

• COUNTER
• SLOWTIME_IN
• SLOWTIME_LATCH
• FASTCLOCK_LATCH
• SLOWTIME_OUT

and the logic to make the stuff happen upon recieving pps and the slowtime.

The pins mapped to the FPGA are

• TIME_CLR
• TIME_CLK
• SPIIN_CS
• SPIIN_CLK
• SPIIN_DATA
• DOUT_CLK
• SPIOUT_DATA
• SPIOUT_CLK
• SPIOUT_CS

Mapping theese pins is pretty easy.

• SPIIN_* is used to recieve the slowtime information from the MICROCONTROLLER
• SPIOUT_* is used to send the SLOWTIME-data to the timing bus.
• DOUT_CLK is a clock of 4Mhz used to generate the SPI clock for SPIOUT_CLK.
• TIME_CLR is connected to the pps pin of the GPS module
• TIME_CLK is connected to the OSCILATOR

This documentation is a wip and probably very obscure and confusing. Please ask armin@hgg.aero if you don't get it and give hints on what to improve.